1. Field of Invention
The present invention relates to a packaging and method of manufacturing the same. More particularly, the present invention relates to a chip packaging and method of manufacturing the same.
2. Description of Related Art
Wafer level chip scale packaging is an advanced way of semiconductor chip packaging. It refers to a process that after all the chips on a wafer are complete, the packaging and evaluation are carried out to every chip on the wafer altogether. After that, the wafer is diced to form a single chip package. The size of a semiconductor chip is ever compact and the wire distribution is much denser. In this case, chip package is more complicated in structure design and manufacture process. The requirement of the electronic components on the chip package, especially its precision and high sensitivity, is tougher. Therefore in the manufacturing process any source of contamination should be eliminated to protect those electronic components. Otherwise their functionality may be compromised. However, maintaining a sterile condition requires great investment in factory equipment, and the manufacturing cost increases as well. Furthermore, mass production is prone to lower yielding rate and product contamination. Accordingly, a more reliable, mass production suitable chip package manufacturing process is an urgent issue in this industry.